1. Technical Field
The present invention relates to an art of designing a three-dimensional integrated circuit, and particularly to an art of designing a three-dimensional integrated circuit in consideration of heat generated within the three-dimensional integrated circuit.
2. Background Art
A three-dimensional integrated circuit has properties that heat is hard to be externally dissipated, compared to a two-dimensional integrated circuit. This makes important to design a three-dimensional integrated circuit in consideration of heat generated within the three-dimensional integrated circuit. For example, there has been known an art of making a circuit layout in the mask layout design phase such that each two vertically stacked chips do not have respective heat generating portions in the corresponding position (see Non-Patent Literature 1).
Also, it is preferable, in a phase prior to the logic synthesis phase, to start such a design as explained above in consideration of heat generated within the three-dimensional integrated circuit. This is in order to reduce repetition of the logic synthesis process and the layout process. In the logic synthesis phase, logic synthesis is performed so as to ensure the operations of the circuit even under assumed conditions in the case where the operating speed is the lowest (worst case), such as even under operating temperature conditions on the entire circuit in the worst case. Here, if the circuit operates under operating temperature conditions better than the assumed operating temperature conditions, an unnecessary performance of the circuit is used. This leads to the consumption of much power and the necessity of a larger area on which the circuit is to be mounted. Such a large performance margin is not preferable in terms of power consumption and size reduction of integrated circuit. In order to avoid such a large performance margin, Patent Literature 1 discloses an art of decreasing a performance margin. Specifically, an integrated circuit includes a plurality of cells that satisfy respective operating conditions, and detects an actual operating temperature of each chip or the entire circuit to switch to a cell that satisfies operating conditions appropriate for the detected operating temperature.